1. Field of the Invention
The present invention relates to a program control method of controlling a conditional branch in an information processing apparatus which processes an instruction by pipeline processing.
2. Description of the Background Art
In an information processing apparatus which processes an instruction by pipeline processing, while instructions are fed to a pipeline and executed one after another, as the instructions are executed overlapping each other, execution of the instructions is realized at a high speed. However, when a conditional branch instruction requires a branch, since an instruction beyond the branch is fetched at a point when the condition is decided, that is, since a branch address is set to a program counter after a branch judgement is made, a wasteful space, namely, a branch hazard is created in the pipeline.
Such a branch hazard is more likely to occur when a condition is met than when the condition is not met. Branch hazards increase one cycle where there is one instruction fetch stage. Branch hazards increase two cycles where there are two instruction fetch stages. Further, branch hazards increase N cycles where there are N instruction fetch stages (N is an optional positive integer.).
One conventional means for solving the problems is a branch method which uses a so-called delay branch, which requires execution of an instruction located at an address which follows a branch instruction in a delay slot to thereby reduce branch hazards in a pipeline. One example of such a conventional branch method is described in Japanese Patent Application Laid-Open Gazette No. 4-127237, for instance.
According to the conventional method as described above, since an instruction in a delay slot is executed during a cycle of a branch hazard, execution cycles of a branch instruction reduce on appearance. However, in a branch method which utilizes a delay branch described above, since there is a restriction on instructions which can be located in a delay slot, or since it is difficult to appropriately assign instructions to a delay slot if branch hazard have a large number of cycles, or for other reasons, it is not possible to effectively reduce branch hazards in all cases.